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VerilogAMS netlist from schematic

acook

Hello, 

I would like to create a verilogAMS netlist from a schematic as a post check and save trigger. I am not trying to do this hiearchtically, I just want to create a verilogAMS view representative of the schematic. I find this useful when creating mixed signals models as you can throw in a few spectre models easiy (like a diode). Usually I have to create a ADE AMS setup, netlist, and steal it from the netlist.vams that spits out.

As far at the netlist form, I would like exactly what ADE in AMS mode generates (with default options).

 I played with the command to create an AMS netlist, but I was unclear on how to set the default options correctly. When I tried one particular schematic, it failed complaing about little endian vs big endian.

Thank you,

Aaron

Parents

  • Andrew,

    What I've done this far is just run the amsNetlist function you mentioned and simply told it the schematic I wanted to netlist.

    The error I mentioned was resolved by setting 'amsDirec.vlog allowDeviantBuses cyclic "warn" ' 

    This may sound rather stupid, but I'm not exactly sure which netlister I am using when I run the amsNetlist command. I know that in my AMS enviorments use OSS/irun which is what I think I want.

     Like I said, my goal here is to generate a verilogams version of a schematic as a post-check and save trigger (there is no ADE enviornment setup in this case). I figured amsNetlist was exatcly what I wanted but when I got that random error about the busses I was concerned about how I was configuring the netlister.

    Thank you,

    Aaron 

Reply

  • Andrew,

    What I've done this far is just run the amsNetlist function you mentioned and simply told it the schematic I wanted to netlist.

    The error I mentioned was resolved by setting 'amsDirec.vlog allowDeviantBuses cyclic "warn" ' 

    This may sound rather stupid, but I'm not exactly sure which netlister I am using when I run the amsNetlist command. I know that in my AMS enviorments use OSS/irun which is what I think I want.

     Like I said, my goal here is to generate a verilogams version of a schematic as a post-check and save trigger (there is no ADE enviornment setup in this case). I figured amsNetlist was exatcly what I wanted but when I got that random error about the busses I was concerned about how I was configuring the netlister.

    Thank you,

    Aaron 

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