Bulk connection of the mos

Please can any one help me to do this code

"Code to detect PMOS and NMOS device in given schematic and change/overwrite bulk connection of PMOS to vdd! and NMOS to vss! "

 Here I'm struck at getting wire information of bulk to source connected mos with respect to PMOS

I have no idea what you're asking here. What does "rewriting the mos bulk connection" mean? Please ask clearer questions, as otherwise it's likely the question will just get ignored if nobody can understand it (as has presumably happened here).

Kind Regards,

Andrew.

I've just found that  you had two separate posts - the second one provided slightly more information than the first. For a start, it showed that you're trying to do this for a schematic. So I merged the two threads.

It's not going to be that easy, because in the picture you showed, there's a wire connecting the bulk to the source. You'd have to find any wire segments which are overlapping the bulk pin, and delete them (probably the best way). Then add a short wire stub with a wire label (vdd! or vss!) to connect them. None of this is going to be that easy - and it's hard for me to explain precisely how to do that without writing the code for you (which I'm not going to do, because it would be quite a lot of work to do a comprehensive solution, especially when I know so little about what you are trying to do and may have misinterpreted it; plus I don't have the time). Also, you might have written most of this already - I don't know.

Regards,

Andrew.

Hi Vaasu,

There is a Solution Article (Solution 11597774) which contains parts of the sort of code that I think you would need for this, it is here. While it is not an exact match for what you are talking about, it does contain code that works from an instance (you have specific instances in mind which you can find in a schematic) and looks at an instance terminal to see if it is overlapped by a wire segment - in your case you are specifically looking for the bulk terminals.

Hopefully the solution code will provide a good starting point?

Best regards,

Lawrence.

 Thanks Andrew for giving feedback......

Whatever you understood the question is right. I choose that method only but I'm deteted the net

 cid= geGetEditCellView()

tid = setof(x cv~>terminals x~>name == "VDD")

foreach( net_id tid~>net

    foreach( fig net_id~>figs

        dbDeleteObject(fig)

      )
)

 Is there any other best way to do this??

  Again while reconnecting and generating label to only  bulk became problem for me. While reconnecting i got bBox of mos by  css()~>instTerms~>net~>figs~>bBox but next how to connect those is problem can anyone help me

 For bulk only I want to create label for that I'm using schCreateWire how to use this command please help me

 Thank you Lawrence for replying..

But I'm not able access that link can please help me to acces that link...

Hi,

I'm attaching the code here. Basically the solution asks if it is possible to prevent users from explicitly wiring up inherited connection pins, and the answer seems to be 'no' but a schematic check procedure (e.g. part of the Check and Save step) might help by identifying and flagging such cases. The code is intended to find wires overlapping pins with inherited connection expressions associated with them - you will need to alter the code to meet your needs, but hopefully this would provide a good start?

Best regards,

Lawrence.