Stats

  • Locked Locked
  • Replies 4
  • Subscribers 143
  • Views 14478
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

StrongGroup suffix in net name

Yaosan Yeo

When I use VXL and gen from source, the transistor generated have weird net name assigned to its source/drain terminals. Rather than named "n1", the net name on the inst term is appended with "_StrongGroup_#" e.g. "n1_StrongGroup_1".

FYI in the schematic I have nfet with m=16, source tied to n2, drain tied to n1. After gen from source, the nfet in layout has source term assigned to net n2, but drain term for each transistor is different: n1_StrongGroup_1, n1_StrongGroup_2, ..., n1_StrongGroup_16.

I would like to know under what circumstances would this happen, what's the purpose of these "StrongGroup" and how to deal with these weird nets. To get back the "parent" net, I could potentially do "car(net->signals)". Still, it is confusing because a net is no longer a simple net and we might need addtional queries to get back the actual net without the StrongGroup suffix.

Tried to look for documentation for this but couldn't find anything.

Parents
  • Andrew Beckett

    Which version of the tools are you using?

    Kind Regards,

    Andrew.

Reply
  • Andrew Beckett

    Which version of the tools are you using?

    Kind Regards,

    Andrew.

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.