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How to identify dummy mos in layout

Venu Ch

Hi All,

I have lot of layouts which contains dummy mos devices but they are not added in schematics. I have to add them in schematic to get LVS clean. It is not generated with VXL. So connectivity is not defined for them. I need to identify dummy transistors in my layout. Could you share your thoughts on it using skill? I am using ic616.

I saw http://www.cadence.com/forums/p/24988/1319633.aspx#1319633 in previous posts. Can we assign default net names for device terminals? If we can assign net names for device terminals then we can able to find dummy.

Thank you,

Chandaka.

Parents
  • Venu Ch

    I completed this code by using some combination of dbgetoverlaps,and, andnot, size commands. Now it is identifing Dummy mos in layout if all terminals are shorted with M1 metal(this is ok because all dummys are connected with m1 only in my layouts). And also I can able to back annotate this dummy in schematic. This is sufficeint fo me except one task. I have to assign dummy terminal net to VDD or VSS.

    In my layouts all terminals of dummy are shorted and connected to either VDD or VSS pin at some where through m2 or m3 metals. 

     For this I have two steps. I am strugling with step1.

    1)Now I have m1 metal id on dummy. I want to get all m1,m2,m3 metals connected to that m1 metal id. (Just like net extraction or saveallmarknet feature,). I can able to get m2 layer which is connected to m1 metal id by using

    via1=setof(x cv~>shapes x~>layerName==v1)

    viaOnMetal=dbLayerAnd(m1metal  via1) ;for quick view i am not writing original syntax.

    m2Lay=dbLayerStraddle(m2Layers viaOnMetal)

    After this I can not able to get remaining metals. Please let me know if you know some other solution?

    2)I have all pins layout. I will check which pin is overlapping with that net and then I will assign that net name in schematic.

     Thanks,

    Chandaka

Reply
  • Venu Ch

    I completed this code by using some combination of dbgetoverlaps,and, andnot, size commands. Now it is identifing Dummy mos in layout if all terminals are shorted with M1 metal(this is ok because all dummys are connected with m1 only in my layouts). And also I can able to back annotate this dummy in schematic. This is sufficeint fo me except one task. I have to assign dummy terminal net to VDD or VSS.

    In my layouts all terminals of dummy are shorted and connected to either VDD or VSS pin at some where through m2 or m3 metals. 

     For this I have two steps. I am strugling with step1.

    1)Now I have m1 metal id on dummy. I want to get all m1,m2,m3 metals connected to that m1 metal id. (Just like net extraction or saveallmarknet feature,). I can able to get m2 layer which is connected to m1 metal id by using

    via1=setof(x cv~>shapes x~>layerName==v1)

    viaOnMetal=dbLayerAnd(m1metal  via1) ;for quick view i am not writing original syntax.

    m2Lay=dbLayerStraddle(m2Layers viaOnMetal)

    After this I can not able to get remaining metals. Please let me know if you know some other solution?

    2)I have all pins layout. I will check which pin is overlapping with that net and then I will assign that net name in schematic.

     Thanks,

    Chandaka

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