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virtuosoDefaultExtractorSetup and auto abutment problem

dshevchenko

In my circuit

.SUBCKT test3 in1 in2 out
*.PININFO in1:I in2:I out:O
MM1 out in1 VDD! VDD! pch m=1 l=60n w=400n
MM0 out in2 VDD! VDD! pch m=1 l=60n w=400n
MM3 net13 in2 GND! GND! nch m=1 l=60n w=200n
MM2 out in1 net13 GND! nch m=1 l=60n w=200n
.ENDS
transistors MM0 and MM1 connected in parallel

In layout i try abut it, but error occured with error marker.

Verify-> Markers->Explain report:

reason:   Warning: Overlap between instance '|M0' with pin 'D' on net 'out'
           and instance '|M1' with pin 'B' on net 'VDD!' creates a short.

Connectivity->Update->Extractor Layout->Options->Extraction->Diagnostic report

*** Constraint Group Diagnostics ***

-----------------
Techfile library: LibMikron_CMOS_065
Constraint group: virtuosoDefaultExtractorSetup
-----------------

WARNING (LCE-2011): Cannot determine the function of layer 'SUB' in constraint group 'virtuosoDefaultExtractorSetup' of technology library 'LibMikron_CMOS_065'. For accurate results during connectivity extraction, set the function to one of the predefined values and reload the technology library.
WARNING (LCE-2012): Cannot find the mask number of layers 'NW OD SUB' in constraint group 'virtuosoDefaultExtractorSetup' of technology library 'LibMikron_CMOS_065'. For accurate results during connectivity extraction, set the layer mask number to a correct value and reload the technology library.

Extractable layers:
  Layer   Function          Mask
  (PO)    poly              1
  (CO)    cut               2
  (M1)    metal             3
  (VIA1)  cut               4
  (M2)    metal             5
  (VIA2)  cut               6
  (M3)    metal             7
  (VIA3)  cut               8
  (M4)    metal             9
  (VIA4)  cut               10
  (M5)    metal             11
  (VIA5)  cut               12
  (M6)    metal             13
  (VIA6)  cut               14
  (M7)    metal             15
  (VIA7)  cut               16
  (M9)    metal             17
  (VIA8)  cut               18
  (M8)    metal             19
  (RV)    cut               20
  (AP)    metal             21
  (NW)    n-type well       --
  (OD)    n-type diffusion  --
  (SUB)   undefined         --

Electrically connected layers:
  (PO)   -> (CO)
  (CO)   -> (PO) (M1) (OD)
  (M1)   -> (CO) (VIA1)
  (VIA1) -> (M1) (M2)
  (M2)   -> (VIA1) (VIA2)
  (VIA2) -> (M2) (M3)
  (M3)   -> (VIA2) (VIA3)
  (VIA3) -> (M3) (M4)
  (M4)   -> (VIA3) (VIA4)
  (VIA4) -> (M4) (M5)
  (M5)   -> (VIA4) (VIA5)
  (VIA5) -> (M5) (M6)
  (M6)   -> (VIA5) (VIA6)
  (VIA6) -> (M6) (M7)
  (M7)   -> (VIA6) (VIA7)
  (VIA7) -> (M7) (M8)
  (M9)   -> (VIA8)
  (VIA8) -> (M9) (M8)
  (M8)   -> (VIA7) (VIA8) (RV)
  (RV)   -> (M8) (AP)
  (AP)   -> (RV)
  (NW)   -> (OD)
  (OD)   -> (CO) (NW)

Standard via definitions:
  DFM_M1_SUB : (M1) -> (CO)   -> (OD)
  M1_SUB     : (M1) -> (CO)   -> (OD)
  DFM_M1_NW  : (M1) -> (CO)   -> (OD) -> (NW)
  M1_NW      : (M1) -> (CO)   -> (OD) -> (NW)
  DFM_M1_OD  : (M1) -> (CO)   -> (OD)
  M1_OD      : (M1) -> (CO)   -> (OD)
  DFM_M1_PO  : (M1) -> (CO)   -> (PO)
  M1_PO      : (M1) -> (CO)   -> (PO)
  DFM_M2_M1  : (M2) -> (VIA1) -> (M1)
  M2_M1      : (M2) -> (VIA1) -> (M1)
  DFM_M3_M2  : (M3) -> (VIA2) -> (M2)
  M3_M2      : (M3) -> (VIA2) -> (M2)
  DFM_M4_M3  : (M4) -> (VIA3) -> (M3)
  M4_M3      : (M4) -> (VIA3) -> (M3)
  DFM_M5_M4  : (M5) -> (VIA4) -> (M4)
  M5_M4      : (M5) -> (VIA4) -> (M4)
  DFM_M6_M5  : (M6) -> (VIA5) -> (M5)
  M6_M5      : (M6) -> (VIA5) -> (M5)
  M7_M6      : (M7) -> (VIA6) -> (M6)
  M9_M8      : (M8) -> (VIA8) -> (M9)
  M8_M7      : (M8) -> (VIA7) -> (M7)
  AP_M8      : (AP) -> (RV)   -> (M8)

Custom via definitions:
  DFM_M1_PPOc : (M1) -> (CO)   -> (PO)
  DFM_M1_NPOc : (M1) -> (CO)   -> (PO)
  M1_PPOc     : (M1) -> (CO)   -> (PO)
  M1_NPOc     : (M1) -> (CO)   -> (PO)
  DFM_M2_M1c  : (M2) -> (VIA1) -> (M1)
  M2_M1c      : (M2) -> (VIA1) -> (M1)
  DFM_M3_M2c  : (M3) -> (VIA2) -> (M2)
  M3_M2c      : (M3) -> (VIA2) -> (M2)
  DFM_M4_M3c  : (M4) -> (VIA3) -> (M3)
  M4_M3c      : (M4) -> (VIA3) -> (M3)
  DFM_M5_M4c  : (M5) -> (VIA4) -> (M4)
  M5_M4c      : (M5) -> (VIA4) -> (M4)
  DFM_M6_M5c  : (M6) -> (VIA5) -> (M5)
  M6_M5c      : (M6) -> (VIA5) -> (M5)
  M7_M6c      : (M7) -> (VIA6) -> (M6)
  M9_M8c      : (M8) -> (VIA8) -> (M9)
  M8_M7c      : (M8) -> (VIA7) -> (M7)
  AP_M8c      : (AP) -> (RV)   -> (M8)

If I comment in rodCreateRect parameters

?termName "B" etc. - no error. But then begin to abut nch and pch transistors, which is unacceptable.

How fix problem?

Code in techfile constraintGroup:

;********************************

; CONSTRAINT GROUPS

;********************************

constraintGroups(

;( group [override] )

;( ----- ---------- )

( "default" nil

) ;default

;( group [override] )

;( ----- ---------- )

( "virtuosoDefaultExtractorSetup" nil

interconnect(

( validLayers (M9 VIA8 SUB AP RV M8 VIA7 M7 VIA6 M6 VIA5 M5 VIA4 M4 VIA3 M3 VIA2 M2 VIA1 M1 CO PO OD NW ) )

) ;interconnect

) ;virtuosoDefaultExtractorSetup

Parents

  • This is a really good description and contains the pertinent data, I wish all requests were so well documented.

    1: reason:   Warning: Overlap between instance '|M0' with pin 'D' on net 'out'
               and instance '|M1' with pin 'B' on net 'VDD!' creates a short.

    2: (OD)   -> (CO) (NW)

    3: ( validLayers (M9 VIA8 SUB AP RV M8 VIA7 M7 VIA6 M6 VIA5 M5 VIA4 M4 VIA3 M3 VIA2 M2 VIA1 M1 CO PO OD NW ) )


    The short is between the bulk (NW) of one instance and the diffusion (OD) of the other - Statement 1

    You are directly connecting NW to OD - Statement 2:

    You are extracting NW and OD - Statement 3

    You may want to remove NW from the valid interconnect layers, that way, it does not get extracted.

    You do not want to abut NMOS and PMOS. The simplest thing to do is add the abutClass property to the abutment pins with different values for NMOS and PMOS. Only pins with the same abutClass will abut if abutClass is assigned.

    Ted

Reply

  • This is a really good description and contains the pertinent data, I wish all requests were so well documented.

    1: reason:   Warning: Overlap between instance '|M0' with pin 'D' on net 'out'
               and instance '|M1' with pin 'B' on net 'VDD!' creates a short.

    2: (OD)   -> (CO) (NW)

    3: ( validLayers (M9 VIA8 SUB AP RV M8 VIA7 M7 VIA6 M6 VIA5 M5 VIA4 M4 VIA3 M3 VIA2 M2 VIA1 M1 CO PO OD NW ) )


    The short is between the bulk (NW) of one instance and the diffusion (OD) of the other - Statement 1

    You are directly connecting NW to OD - Statement 2:

    You are extracting NW and OD - Statement 3

    You may want to remove NW from the valid interconnect layers, that way, it does not get extracted.

    You do not want to abut NMOS and PMOS. The simplest thing to do is add the abutClass property to the abutment pins with different values for NMOS and PMOS. Only pins with the same abutClass will abut if abutClass is assigned.

    Ted

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