Parameterized PCell Schematic

If you have a component (probably not a pcell) which doesn't handle parameterization because of poorly written CDF callbacks (see my article The Dangers of CDF Callbacks), then wrapping it in a pcell will not help you. PCells are evaluated once per variant, not once per instance (and certainly not once per occurrence). In order for what you are asking for to work, it would require pcells to be evaluated once per occurrence - each hierarchical path down through the hierarchy would need to be individually evaluated so that the set of parameter values could be found for that particular path through the hierarchy, and then the CDF callbacks called with actual numbers rather than passed parameters (either NLP or pPar). It would also then require the netlisters to duplicate hierarchical blocks to ensure each leaf occurrence was unique.

Since pcells are only evaluated once per set of unique parameter values (which makes them vastly more efficient), and this hierarchical expansion during netlisting does not occur either, there's no way you can make this work.

I generally stress to PDK providers that making derived parameters dependent upon CDF callback evaluation is rather limiting in terms of parameterization - so you might want to push back on the PDK provider.

That said, if using ADE XL, you can use the Variables and Parameters assistant to add sweeps on component values which are governed by CDF callbacks; the CDF callbacks are then evaluated as a pre-cursor to netlisting for each point in the sweep. Note that this only gives you the ability to sweep an instance in a cell rather than a hierarchical occurrence, but that covers the majority of requirements for most people.

Kind Regards,

Andrew.

Thank you for your response Andrew. I actually stumbled upon that article a few days ago and found it very informative.

I should mention that my goal here is to have a single schematic for multiple layouts, not just optimization in simulation. I find that within our libraries, we often create duplication just to change something silly that could be parameterized if the functionality existed. For example I want to have a single OTA core that I can just tell it what I want for the diff pair W/L. The layout engineer would then just make an alternate layout with those parameters. Would this even be feasible with the proper PDK setup?