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Extract nets connected to PCELLS in layout

typon

Hi,

I'm trying to measure the path length of any rectangles or paths that are attached to my transistors using SKILL. For this, my approach is to try to get all nets connected to a transistor (or any other PCELL for that matter), identify which port of the transistor they are attached to and measure their length. Is such a thing possible? If so, can anyone please illuminate how it could be done?

I drew up a figure quickly to show you what I mean.

If this was my layout for example, the output of the script should be:

1. NET123: Metal1, S, 2um.

2. NET456: Metal1, D, 2.9um.

Is this possible to do? Can you programmatic figure out which nets are connected to which port of a transistor, and tell which metal they are in? From looking at other posts, it seems possible that you can figure out the length so that is probably not an issue.

Thanks for your help.

Hassan

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  • theopaone

    You should be using an extraction tool such as QRC.

    The command you want to use is search command dbGetTrueOverlaps. You have to find the shape on the pin in the instance and use that as the bounding box for the search. From there, you have to search the overlapping shapes for connection layers such as the same metal or vias and continue through the hierarchy. All this is done for you by an extraction tool.

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  • theopaone

    You should be using an extraction tool such as QRC.

    The command you want to use is search command dbGetTrueOverlaps. You have to find the shape on the pin in the instance and use that as the bounding box for the search. From there, you have to search the overlapping shapes for connection layers such as the same metal or vias and continue through the hierarchy. All this is done for you by an extraction tool.

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