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ERROR (VACOMP-1008), ERROR (SFE-91), ERROR (SFE-46) in POSTSIM

Duy Hien

Hi everyone,

My system: CentOS release 5.8 (Final) 32 bit, Cadence IC615, MMSIM 13 sub-version  13.1.1.480.isr15

I tested my system by a simple circuit (2 caps) and I could run postsim in this simple circuit.

So I moved to my design. I had no problem when I ran schematic simulation. But I got problem when I tried to run postsim. Here are problems:

Warning from spectre during AHDL read-in.
WARNING (VACOMP-2397): Compilation failed when using pipe build. Bytecode flow will be used for encrypted VerilogA, and normal file compilation will be used for unencrypted VerilogA.

Compiling ahdlcmi module library.

Error found by spectre during AHDL read-in.

ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB//bsource.va.bsource_45bff1.ahdlcmi/Linux/../ahdlcmi.out for details. If the compiler ran out of memory, use 'setenv CDS_CMI_COMPLEVEL 0', and try again. Otherwise, contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.
ERROR (SFE-91): Error when elaborating the instance bsource_45bff1. Simulation should be terminated.

Opening directory input.ahdlSimDB/ (775)
Opening directory input.ahdlSimDB//bsource.va.bsource_c2745e.ahdlcmi/ (775)
Opening directory input.ahdlSimDB//bsource.va.bsource_c2745e.ahdlcmi/Linux/ (775)
Compiling ahdlcmi module library.

Warning from spectre during AHDL read-in.
WARNING (VACOMP-2397): Compilation failed when using pipe build. Bytecode flow will be used for encrypted VerilogA, and normal file compilation will be used for unencrypted VerilogA.

Compiling ahdlcmi module library.

Error found by spectre during AHDL read-in.
ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB//bsource.va.bsource_c2745e.ahdlcmi/Linux/../ahdlcmi.out for details. If the compiler ran out of memory, use 'setenv CDS_CMI_COMPLEVEL 0', and try again. Otherwise, contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.
ERROR (SFE-91): Error when elaborating the instance bsource_c2745e. Simulation should be terminated.
Error found by spectre during hierarchy flattening.
ERROR (SFE-46): "/tools/cadence/pdk/IBM_PDK/cmrf7sf/V2.0.0.2AM/Spectre/models//diodenwx.scs" 47: `gleak': An instance of `bsource_45bff1' can have at most 0 terminals (but has 2).

I did search and found some thread but I cannot fix. And I wonder why the problems occurred in postsim of a complex circuit?

Please help me.

Parents

  • Looking back at the top of your post, the issue is that you are running on a 32-bit OS. Since MMSIM11.1 we only support 64-bit OS (RHEL5 and above).

    Some of the utilities (e.g. cdsPerl) only exist in 64-bit form, and because of that, it is failing to build the Makefile, and then failing to compile the bsource or Verilog-A models.

    Given all reasonable recent (and even not-so-recent) hardware should be 64-bit, installing a 32-bit OS makes no sense and will lead to issues. Cadence ended support for RHEL4 and 32-bit OS in 2011 (the latest platform roadmap starts from 2012 but you can see only 64-bit OS listed):

    Regards,

    Andrew.

Reply

  • Looking back at the top of your post, the issue is that you are running on a 32-bit OS. Since MMSIM11.1 we only support 64-bit OS (RHEL5 and above).

    Some of the utilities (e.g. cdsPerl) only exist in 64-bit form, and because of that, it is failing to build the Makefile, and then failing to compile the bsource or Verilog-A models.

    Given all reasonable recent (and even not-so-recent) hardware should be 64-bit, installing a 32-bit OS makes no sense and will lead to issues. Cadence ended support for RHEL4 and 32-bit OS in 2011 (the latest platform roadmap starts from 2012 but you can see only 64-bit OS listed):

    Regards,

    Andrew.

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