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ASSURA DRC- ERROR

Anum Khan

Hi,

I am exploring two stage CMOS OP AMP in Cadence.

I managed to make the schematic and layout but i am stuck in ASSURA DRC . I have tried to remove the error but it is not resolved.

Error is shown in the picture.

Please help me how can i remove this error.

Regards.

Parents
  • Presumably you need to increase the TAP AREA to be above 0.4992! I am assuming this is related to the area of the substrate or well tap (I can't see from the picture what it is). Anyway, this is a wild guess because you've given no information as to the technology you're using - the error is specific to the rules you're using and not something that is just coming out of the tools. You might also want to look in the DRM (Design Rule Manual) for your technology to see if that explains what the requirement is.
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  • Presumably you need to increase the TAP AREA to be above 0.4992! I am assuming this is related to the area of the substrate or well tap (I can't see from the picture what it is). Anyway, this is a wild guess because you've given no information as to the technology you're using - the error is specific to the rules you're using and not something that is just coming out of the tools. You might also want to look in the DRM (Design Rule Manual) for your technology to see if that explains what the requirement is.
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