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Reading simulation results using Skill

ChrisEAS

Hi,

I am looking for a Skill way of reading the signal names that have been saved during an ADE-XL simulation. I am aware of the outputs() function. However, in my case this function exits with a regEx error message - I guess due to some slightly unconventional naming of my lib and cells. However, I don't want to rename my design. Therefore I am looking for an alternative to the outputs() function. Using the Results Browser, I am able to see all my signals. Can I do this with Skill too, without using the outputs() function?

Thanks

Chris

  • Hi Chris,

    If you get an error, you should report this to customer support because that's a bug.

    Can you try using outputs(?map nil) to see if that works instead?

    Regards,

    Andrew.

  • Andrew,

    Thanks, this option seems to work! Is it still a bug that should be reported?

    Regards,
    Chris

  • Hi Chris.

    Yes, it's still a bug. I suspect something is breaking in the mapping code where it's trying to reverse map the simulator names in the  output database to the schematic names, and that may be related to some unusual character you have - but it really shouldn't break. If it's a legal Virtuoso name, it should map correctly.

    Regards,

    Andrew

  • Lib and cell both start with a digit and also got a few underscores in the middel. I will report it to customer support to get it fixed. In the meanwhile, is it safe to use map=nil? What does the option do anyway?

    Regards,
    Chris

  • Hi Chris,

    Yes, it's safe. 

    Normally the result of outputs() is a list of schematic names. This means that the names start with a "/", use "/" as the hierarchy separator, and the names appear exactly as they do in the schematic. If you ask for a result called (say) "/I1/I2/net3" then it will translate that to the corresponding netlist name to really retrieve the result. Now, the names in the result database are in terms of whatever things were called in the simulator, and with spectre, the hierarchy separator is ".". Any illegal characters (in spectre conventions) will be mapped, as will any reserved words. So a simple case like "/I1/I2/net3" would just end up as "I1.I2.net3", but a more complex case could map in a more complex way.

    Anyway, when you call outputs(?map nil) it doesn't do the reverse mapping and just outputs the names precisely as they appear in the result database - using the simulator names. So you'd see things like "I1.I2.net3" in the output list.

    When you request a signal (e.g. with the v() function, getData() function etc), then if the name begins with a "/" it is assumed to be a schematic name and will go through the mapping process. Otherwise it's treated as a simulator (or netlist) name.

    So if I do:

    v("/I1/I2/net3")

    it would give the same result as doing:

    v("I1.I2.net3")

    Regards,

    Andrew.

  • Andrew, thanks for the explanation. Although I am afraid the problems may just got shifted from the outputs() to the v() function. But I will check that... Thanks anyway.

    Regards,
    Chris

  • Hi Chris,

    I'm not sure why the problem would occur with the v() function if you use the netlist name in the argument to v(), as then no mapping would get done. So you can just use v("I1.I2.net3") for example. In fact, even if you use the schematic names v("/I1/I2/net3") it may still work because it's a different mapping function - it's going in the opposite direction - so maybe the problematic code only affects one direction.

    Regards,

    Andrew.

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