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  3. SKILL for Substrate Integrated Waveguide layout

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SKILL for Substrate Integrated Waveguide layout

jack.holloway
jack.holloway over 8 years ago

Folks,

I've been looking for some generic custom SKILL (using virtuoso, IC6.1.7) to generate arrays of vias based on PDK-defiend minimum via spacing in a variety of different areas (polygons) between arbitrary metal layers, to include metal slotting for large connected areas. I'm building a number of 3D structures, include SIWs, in the BEOL and hand-generating these arrays for each structure is quite time consuming. Any pointers on where I should be looking?

Regards,

Jack

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  • skillUser
    skillUser over 8 years ago
    Hi Jack,

    There are many factors involved but I have a few suggestions. First, you can use dbLayerTile() to fracture a polygon into trapezoids, you can then further process any that are not rectangular into approximations of rectangular areas. From the rectangular areas you might then use something like dbCreateViaShapeArray() or dbCreateVia() with appropriate rows, columns, spacing etc. For any slotted areas you could use dbCreateOverlaps() to identify areas that should be free of vias/via shapes and remove those using dbDeleteObject() (i.e. delete them after they were created, rather than trying to decide up front if they should be created). You might need to align vias/cut shapes and so you could use rodAlign() or leAlign() (don't use the latter in a PCell, if you are creating PCells). You might use something like techGetLayerFunctions() to identify the metals and vias between in a more generic fashion than hard-coding the values. Similarly you might use techGetSpacingRule() and techGetOrderedSpacingRule() to get the information on spacings etc. more generically.

    Hopefully this helps?

    Best regards,

    Lawrence.
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