Stats

  • Locked Locked
  • Replies 3
  • Subscribers 143
  • Views 13704
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Establish connectivity on a text purpose layer to traverse hierarchy.

snee

We have several layouts where the designers did not place pins on their nets, but rather tagged them with text layers to pass LVS. We're looking for a way to use the existing text layers to propagate connectivity through hierarchy, without having to edit the underlying layout and place pins. Also, we do not want to simply generate the pins on the top level cell with leHiCreatePinsFromLabels(), but would rather modify the text layer to inherit the properties of a pin.

Does anyone know of a method to do this?

Thanks.

  • I don't think I really understand what you're trying to do. If you want connectivity in the database throughout the hierarchy, aren't you going to have to edit those cellViews anyway? In which case, why not add the pins?

    If you're talking about making sure that LVS recognises the text, that's a different question (in which case knowing the LVS tool would be important).

    Perhaps you can clarify your objective?

    Regards,

    Andrew

  • Standard cells were created without pins. Nets in those cells were tagged with text layers representing the net names to pass LVS.
    Those cells are then used in other top level cells but connectivity does not propagate from lower level standard cell.
    The user has asked to allow text layers to act like pin layers so that connectivity can propagate up throughout hierarchy.
    A major requirement is that user does not want to edit lower level standard cells to add pins.

  • If you're talking about VLS XL, then the answer is almost certainly "no". There is some capability with Connectivity->Update Binding (setting the extractor depth to greater than 0, setting stop layers using something like lceAddSimpleStopLayers("gpdk090" list(list("Oxide" "Poly"))) if they're not in the tech file), but this isn't going to work if there aren't instances of transistors in the standard cells (most standard cell libraries have flat shapes in my experience). This works by shape chasing down through the hierarchy - it's not using the labels in the cells.

    By far the best solution is to add pins - potentially you could create abstracts for the standard cells, extract the pins when you do that, and then switch the standard cell instances to use the abstracts using remaster instances. Then do the extraction (or update binding) and then switch back again.

    How successful this will be depends on the state of the data. I'd suggest you contact customer support so that an Application Engineer can look at this with you.

    Regards,

    Andrew.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.