$sscanf in verilog-A

Hi,

Following is my verilog A code. I am tying to append an integer to string and assign it to a string using $sscanf. 

string filename;

string ext;

integer file_num;

analog begin

@(initial_step) begin

file_num=1;

ext="csv";

filename=$sscanf("%d.%s",file_num,ext);

end

end

I get error while saving the file. Error: Missing arguments.

 ERROR : "filename=$sscanf("%d.%s",file_num,ext)<<--?

Encountered invalid type conversion for `filename' (`integer' to `string'). Check the validity of conversion and try again.

I also tried string concatenation

filename={file_num,ext};

For the above statement file_num is defined as string and file_num="1" is the initialization statement. ext is initialized with ".csv". I get syntax error.

Please let me know what is wrong with my code. 

I am using virtuoso 6.1.6. mmsim 14.1.0.