A procedure to re-name and unify net and module port names in a design?

I have inherited a large number of cells designed by different people with different degrees of naming discipline, which makes the designs hard to read and understand.

I would like to select a signal and  re-name it in the design in order to unify and enforce a signal naming standard.

The renaming should stop when it encounters a library primitive (link, transistor, etc), automatically checking out the schematic and symbol all cells that this net touches. (Also check and saving it)

I imagine this is possible using SKILL code, but I am new to SKILL and don't know the best place to begin.

For example, I want this:

To become this by running the procedure on the selected net.: