What is default port order, and how to create it?

So for everyone who confused with portOrder and CDF termOrder that is what I was able to figure out.

portOrder property
Each view can have portOrder property.
Schematic and symbol views, when created from scratch, created without portOrder property.
Text views as VerilogA VerilogAMS etc. created with portOrder property also when created from scratch.
When cell view created using "Create Cellview from Cellview", portOrder property created on new(created) cellview (Article 20302001).

If schematic or symbol created from text view (VerilogA etc.) using "Create Cellview from Cellview",
The portOrder property will be set according to the order of ports in the definition of source text view.
If symbol created from schematic view using "Create Cellview from Cellview", portOrder property will be set as follows:
Default portOrder is: output/inputOutput/input when for each type ports alphabetically sorted (Article 20302001)

CDF termOrder property
CDF can have termOrder property for each simulator
If "auCore.misc" "createCDFtermOrder" set to t (default) CDF termOrder will be created automatically for all simulators when schematic view created.
Default order of ports is alphabetic

Spectre netlisting
If neither CDF termOrder property for Spectre, nor portOrder property of a schematic set, the alphabetic port order will be used by netlister.
If it is only CDF termOrder property for Spectre, this termOrder will be used by netlister
If schematic view (or another used view) termOrder is set, it will be used regardless of CDF termOrder property

Verilog-AMS netlister
Seems to always use output/inputOutput/input port order regardless of CDF termOrder or portOrder property.

Views creation
When text view (VerilogA etc.) created from a schematic using "Create Cellview from Cellview", ports created in flowing order:
If portOrder property isn't set, default portOrder will be used ( output/inputOutput/input when for each type ports alphabetically sorted)
If portOrder property is set, port order from portOrder property will be used

SKILL functions
almGetTerminalList(lib cell ?tool simulator)
Can be used to read CDF termOrder property for specific simulator

schGetPinOrder()
If portOrder property isn't set, function will return default portOrder ( output/inputOutput/input when for each type ports alphabetically sorted)
If portOrder property is set, function will return port order from portOrder property

artGenerateHierSymbolCDF()
Function will reset CDF termOrder property for all simulators to alphabetic, same as created authomatically if "auCore.misc" "createCDFtermOrder" set to t

I've been meaning to reply to this thread for a while - just hadn't got to it.

In general, the portOrder is not that important nowadays and it's debatable whether all the consistency checks are necessary (I've got a request to disable them by default). The only thing that really uses portOrder is the Verilog netlister (non-ADE netlisters, in other words) and even then it's really only needed for leaf cells if you're netlisting by order (implicit) rather than by name (explicit). For other levels it may get used, but if it's inconsistent between views that's not critical because it should always use the same portOrder for both the instance (the caller) and the definition (the callee, i.e. the module/subckt etc).

ADE netlisters use the CDF termOrder. Again, this is important for leaf (i.e. stopping) views because they need to know how to connect with the right order to some external or built-in component in the simulator. For intermediate levels in the hierarchy it's used as a guide, but since both the caller and callee are netlisted consistently it's not so critical. If the termOrder is inconsistent with the terminals on the views (e.g. if there are extra or missing terminals) it is ignored (with a warning) and the default order is used instead (which is OK, because it's consistent). The cdsenv variable:

auCore.misc  updateCDFtermOrder boolean t

can be set so that any updates to the pins on symbols will trigger an update of the termOrder in the CDF to make it consistent which eliminates these warnings.

Note that the termOrder in the CDF is per cell, but then there is also something called "view-specific CDF" which is another bit of information in the CDF which allows the terminal order to be different for different views. This is important when there are textual views involved - imagine that a cell has a schematic and two veriloga views - and the veriloga views were written with inconsistent terminal orders. This allows for the netlister to ensure that the instance uses the correct order. The Tools->CDF->Edit CDF form doesn't show the view-specific CDF but if you dump the Base CDF you can see it. Also, the alm functions you mention will deal with view-specific CDF.

Hope that helps in addition to what you've found.

Regards,

Andrew.

I've been meaning to reply to this thread for a while - just hadn't got to it.

In general, the portOrder is not that important nowadays and it's debatable whether all the consistency checks are necessary (I've got a request to disable them by default). The only thing that really uses portOrder is the Verilog netlister (non-ADE netlisters, in other words) and even then it's really only needed for leaf cells if you're netlisting by order (implicit) rather than by name (explicit). For other levels it may get used, but if it's inconsistent between views that's not critical because it should always use the same portOrder for both the instance (the caller) and the definition (the callee, i.e. the module/subckt etc).

ADE netlisters use the CDF termOrder. Again, this is important for leaf (i.e. stopping) views because they need to know how to connect with the right order to some external or built-in component in the simulator. For intermediate levels in the hierarchy it's used as a guide, but since both the caller and callee are netlisted consistently it's not so critical. If the termOrder is inconsistent with the terminals on the views (e.g. if there are extra or missing terminals) it is ignored (with a warning) and the default order is used instead (which is OK, because it's consistent). The cdsenv variable:

auCore.misc  updateCDFtermOrder boolean t

can be set so that any updates to the pins on symbols will trigger an update of the termOrder in the CDF to make it consistent which eliminates these warnings.

Note that the termOrder in the CDF is per cell, but then there is also something called "view-specific CDF" which is another bit of information in the CDF which allows the terminal order to be different for different views. This is important when there are textual views involved - imagine that a cell has a schematic and two veriloga views - and the veriloga views were written with inconsistent terminal orders. This allows for the netlister to ensure that the instance uses the correct order. The Tools->CDF->Edit CDF form doesn't show the view-specific CDF but if you dump the Base CDF you can see it. Also, the alm functions you mention will deal with view-specific CDF.

Hope that helps in addition to what you've found.

Regards,

Andrew.

Anderew,

thank you for the reply.

Indeed the problems appear only when we used Verilog netlister of simulated with dspf files.

But, I noticed that in last versions of Spectre it can properly take port order from DSPF. (Still, it is confusing because port order is taken from DSPF when "sch" option selected in the DSPF options)

BTW how can I turn off port order consistency checks?

Alex.

Hi Alex,

You can't, currently. There's CCR 1089308 (with a couple of duplicates) asking for it to be turned off and if anyone really wants it to provide an option to turn it back on again via a setting.

You might want to contact customer support to request a duplicate be filed to help increase the likelihood of it being implemented sooner rather than later.

Regards,

Andrew.