PVS QRC problem in Finfet Cadence GPDK

Hi,

I have recently started to play with Cadence Finfet GPDK. I design a simple inverter and run Spectre simulation on schematic and it is fine. However, the documents are limited and I did not find enough information from the PDK doc. 

Would you please let me know if there are more documents available for this PDK? If there is a layout design example I can access?

After a while I could be able to pass PVS LVS but when I try PVS QRC without any parasitic (NO RC) the generated netlist for extracted layout is different from the schematic. I have provided schematic and extracted layout (by QRC) netlists as below:

************** Schematic netlist **************

 subckt test_schematic GND In Out VDD

    NM1 (Out In GND GND) cds_ff_mpt_n1hvt l=18n nfin=2 nf=1 m=1 ngcon=1 \

        asej=6.528e-15 adej=6.528e-15 psej=2.32e-07 pdej=2.32e-07 lrsd=18n

    PM1 (Out In VDD VDD) cds_ff_mpt_p1hvt l=18n nfin=2 nf=1 m=1 ngcon=1 \

        asej=6.528e-15 adej=6.528e-15 psej=2.32e-07 pdej=2.32e-07 lrsd=18n

ends test_schematic

************** Extracted layout netlist **************

  subckt test_schematic_av_extracted GND In Out VDD

    PM1 (X1\|10 In VDD X1\|11) cds_ff_mpt_p1hvt l=1.8e-08 nfin=2 nf=1 m=1 \

        ngcon=1 asej=1.904e-15 adej=1.904e-15 psej=3e-07 pdej=3e-07 \

        lrsd=18n

    NM1 (Out In\@1 X0\|9 GND) cds_ff_mpt_n1hvt l=1.8e-08 nfin=2 nf=1 m=1 \

        ngcon=1 asej=1.904e-15 adej=1.904e-15 psej=3e-07 pdej=3e-07 \

        lrsd=18n

ends test_schematic_av_extracted

It can be seen that transistors PM1 (or NM1) is connected to different terminals compared to schematic ones. For example, PM1 is connected to (Out In VDD VDD) in the schematic while in the extracted layout it is connected to (X1\|10 In VDD X1\|11).

Would you please let me know if you have any idea about this problem?

Thanks for your help