I have a verilog-A component that converts an integer (passed as an instance CDF parameter) into an electrical digital bus value, with a fixed number of bits (see code below).It works well and now I'd like to make it "truly" parametric, so that the bit width can also be an instance parameter which, when modified, changes the number of bits of the output bus ("dynamic termOrder"), much in the same way like some analogLib components are able to do (e.g. "mtline" component, which dynamically changes the number of lines when varying the CDF parameter "n").To implement this behavior, which modifications would I need to do......in the CDF?...in the symbol view? (how does "mtline" achieves its cool "dynamic" symbol update according to the number of lines?)...in the verilog-A code?...anywhere else?Thanks in advance for any help!Best regards, Jorge.
`include "discipline.h"`define NBITS 8(* instrument_module *)module DEC2BIN__8bit (DOUT);output [`NBITS-1:0] DOUT;voltage [`NBITS-1:0] DOUT;parameter integer CODE= 0 from [0:(1<<`NBITS)-1];parameter real VDD = 1;parameter real VSS = 0;genvar i;analog begin for (i=0; i<`NBITS; i=i+1) begin V(DOUT[i]) <+ (CODE & (1<<i)) ? VDD : VSS; endendendmodule
See this example in an article that I wrote: How to create a VerilogA model of a DAC with a variable width bus input
It's slightly complicated because of the need for a pcell for the symbol and "shadow" database in the VerilogA view, but the article explains how to do that with a worked example.