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Virtuoso: how to create a (truly) parametric component (i.e. with "dynamic" termOrder)?

MurimGomes

I have a verilog-A component that converts an integer (passed as an instance CDF parameter) into an electrical digital bus value, with a fixed number of bits (see code below).

It works well and now I'd like to make it "truly" parametric, so that the bit width can also be an instance parameter which, when modified, changes the number of bits of the output bus ("dynamic termOrder"), much in the same way like some analogLib components are able to do (e.g. "mtline" component, which dynamically changes the number of lines when varying the CDF parameter "n"). easybib
 
To implement this behavior, which modifications would I need to do... fedloan

...in the CDF?
...in the symbol view? (how does "mtline" achieves its cool "dynamic" symbol update according to the number of lines?)
...in the verilog-A code? irs.gov
...anywhere else?

Thanks in advance for any help!

  • Andrew Beckett

    There are multiple pieces to this. The first is having a PCell (Parameterised Cell) for the symbol, which allows the symbol to be generated using SKILL code which is executed for each variant of the parameters set on the instance. Then typically there needs to be some custom netlist procedure so that it netlists correctly. There was a similar recent question about this part: custom pcell for symbol/schematic that has variable number of terminals

    Doing all this with a VerilogA model is slightly trickier still.

    The good news is that I've written an article on this! It can be found here: How to create a VerilogA model of a DAC with a variable width bus input

    Regards,

    Andrew.

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