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  3. How to create PDK device and how to view external simulation...

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How to create PDK device and how to view external simulation result in ADE

HaolinCong
HaolinCong over 5 years ago

Hi guys,

Here I am working with a new technology. I wish I could implement two things :

1. How can I create the device like 'nmos' in the PDK with some parameters so that I can use to build the schematic?

(After that, I will write my own skill script to 1. format and export the netlist , 2. call the simulator to simulate the netlist. This has been done. )

2. Then, I want to import the simulation result which is a .csv like format file, to virtuoso to check the result. However, I found it can only import DB format file and it is not a readable format. So my second issue is how can I import external simulation result to virtuoso or ADE?

Thank you very much for your help,

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  • Andrew Beckett
    Andrew Beckett over 5 years ago

    This is rather a big subject fro the community forums - you would be better off contacting customer support. You may find this document on the support site useful: Cadence Process Design Kits & Rule Decks (PRD) Methodology Guide for IC6.1

    For the second question, ViVA can read in CSV files as data (you can open them in the results browser), or you can use the getAsciiWave function in the calculator to read columnar data and then plot it.

    Andrew.

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  • HaolinCong
    HaolinCong over 5 years ago in reply to Andrew Beckett

    Than you so much Andrew. For the first question, I find an alternatively method. Actually I don't need a real PDK library. What I need is just a user friendly way to build the circuits and pass the parameters to my netlist. So I think I could just simply use a verilogA fake device. For the second question, I tried CSV but failed. Then I realize there is a VCSV format I could use and it works. I don't know why csv file is not working, maybe it's because the version is old? I am using virtuoso 6.1.6. But anyway, my problem get solved.

    Thank you again.

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  • Andrew Beckett
    Andrew Beckett over 5 years ago in reply to HaolinCong

    That sounds a bit odd (for the first point) - I don't know what you mean by a "VerilogA fake device". You could just use the nmos4 and pmos4 from analogLib, give it the name of the model you have (assuming you have a model) and then include the model file via Setup->Model Libraries in ADE. If you don't have a model file, I'm not sure what you'd be trying to achieve anyway (you could just use gpdk045 or similar from http://pdk.cadence.com  to experiment with a design).

    Anyway, sounds as if by some means or other you've solved your problem.

    Regards,

    Andrew.

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  • HaolinCong
    HaolinCong over 5 years ago in reply to Andrew Beckett

    Maybe I didn't make it clear. I will need to use another simulator which wasn't installed in cadence to simulate the circuits. So here I just want to 'borrow' the convenient schematic editor to help me create an ASCII netlist file to be simulated by other tools. That's why I am saying a 'fake' device.

    Thanks a lot. I appreciate your help.

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