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DSPF with veriloga

anikwag

Hi,

I have a query related to the use of DSPF of a design with veriloga model of a subblock in the same design. I am working on a macro which has a huge counter, so to speed up the simulations we use a Veriloga model of the counter and run schematic based simulations. Now, if I am giving dspf as an input with the veriloga model for the counter block and the dspf is mapped to the schematic, then will the tool take the dspf for the rest of the blocks in the design and veriloga for the counter block. Is my understanding correct?

Que 2) Is there a faster way to simulate the dspf without veriloga ? I have tried using APS++ and keeping liberal settings with post layout optimizations turned-on but as the counter is operating at 1GHz frequency and will count upto 4ms of time. Hence, its taking huge time in simulating the design. I have also tried using hspice simulations which gives me results in 3-4 days. But Is there an option in adexl where i can reduce the run time in polo simulations using virtuoso?

Thanks and Regards,

Aniket 

  • It's not entirely clear what you have in DSPF and what you have in Verilog-A. It rather depends on whether the DSPF has a blackboxed instance of the block for which you have verilogA, or whether it's extracted down to transistor level. If including the DSPF via the Setup->Simulation Files form you may also need to specify the blackbox for the cells in question.

    To make it faster, you might want to consider using Spectre X.

    Andrew.

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