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How to prevent design rule error (physical property) in virtuoso schematic?

jhpark

I am trouble with setting the design constraints for the schematic (virtuoso 6.1.7, ADE Explorer).

For example, for editing MOSFET properties I typed 151.34343nM for Width (which is illegal for the given process, 140nm , 145nm 150nm .. are acceptable) and the cadence tool does not alarm or warn the illegal properties.

If I type 151.34343nM for the width, then I want the tool warns about that and automatically change the width closest available value (150 nM for the example).

How to let the tool know the design rule and prevent such a problem? 

Parents Reply
  • in reply to Kevin Buck

    Thanks Kevin for referring to that (I wrote the article). However I think the challenge here is that whether this will help is dependent upon whether the CDF callbacks for the MOS devices in the PDK have callbacks already that restrict the allowable values for the component. Whether they do or not is dependent on how the foundry has chosen to implement the PDK - so you might need to speak to the foundry to implement this.

    Regards,

    Andrew

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