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Adding Power/Ground/Signal markers to *PININFO in auCDL netlist.

JameelAhmed

Hi,

When I CDL out a schematic and check the "Display Pin Information", for example, the netlist contains the *PININFO for each ckt as shown below

.SUBCKT AERC.6.0  X_OUTIN_A IN_B IN_C VDD
*.PININFO IN_A:I IN_B:I IN_C:I X_OUT:O VDD:B
XI1 IN_A net12 IN_B X1 net13 net14 / AERC.6.0.sub
XI0 X1 net15 net18 IN_C VDD  X_OUT/ AERC.6.0.sub
.ENDS

The *PININFO includes the direction of the pin for each of the in, in this example the IN_A, IN_B and IN_C are input pins and GND is an output pin and VDD is an  inputOutput/Bi directional pin.

In addition to the pin direction, I would also like to include the signalType information in the netlist, for example in the schematic I can chose the signaltype on the pin as power, ground, signal, clock etc.

Could you please let me know how I can go about doing this?

Ideally, I would like to output the *PININFO line as. Basically I want to concatenate the signalType of the pin after the pin direction.

*.PININFO IN_A:I:signal IN_B:I:signal IN_C:I:signal X_OUT:O:ground VDD:B:power

I would really appreciate any help.

Thanks,

Jameel

 

Parents
  • JameelAhmed

    After doing more search, I found the following in the Cadence® Analog Design Environment user guide.

    PININFO for Power and Ground Pins
    If you want power and ground pin names to appear with :P and :G, respectively, in the
    *.PININFO line in the CDLOut netlist for non-global signals, you can specify this with the
    cellViewPowerPins and cellViewGroundPins properties.
    For example, you may have four pins in the cellView, namely A, B, VSS, and VDD, and you want
    the PININFO lines to appear as follows:
    .SUBCKT test A B VDD VSS
    *.PININFO B:P VSS:G A:G VDD:P
    .ENDS
    From the schematic cellView, click Edit – Properties – CellView. Click Add in the User
    Property section and add the following properties:
    cellViewPowerPins, with Type as ilList and Value as ("B" "VDD")
    cellViewGroundPins, with Type as ilList and Value as ("A" "VSS")
    Then, check and save the cellView.
    When you run the netlister, CDL Out checks for two properties of the type ilList in the
    cellview, namely cellViewPowerPins and cellViewGroundPins, and generates the
    netlist according to information specified with them. The PININFO lines in the netlist appear
    as mentioned above.

Reply
  • JameelAhmed

    After doing more search, I found the following in the Cadence® Analog Design Environment user guide.

    PININFO for Power and Ground Pins
    If you want power and ground pin names to appear with :P and :G, respectively, in the
    *.PININFO line in the CDLOut netlist for non-global signals, you can specify this with the
    cellViewPowerPins and cellViewGroundPins properties.
    For example, you may have four pins in the cellView, namely A, B, VSS, and VDD, and you want
    the PININFO lines to appear as follows:
    .SUBCKT test A B VDD VSS
    *.PININFO B:P VSS:G A:G VDD:P
    .ENDS
    From the schematic cellView, click Edit – Properties – CellView. Click Add in the User
    Property section and add the following properties:
    cellViewPowerPins, with Type as ilList and Value as ("B" "VDD")
    cellViewGroundPins, with Type as ilList and Value as ("A" "VSS")
    Then, check and save the cellView.
    When you run the netlister, CDL Out checks for two properties of the type ilList in the
    cellview, namely cellViewPowerPins and cellViewGroundPins, and generates the
    netlist according to information specified with them. The PININFO lines in the netlist appear
    as mentioned above.

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