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Could Virtuoso VXL or SKILL code report missing via on the same net

mctang21 over 3 years ago

M1 (net VDD) and M2 (net VDD) polygon overlaps without via.

1. Could Virtuoso VXL report missing via ?

2. Any existing SKILL code reports missing via.

If not, I need to implement it in DRC flow.

Thanks,

ManChak

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AurelBuche over 3 years ago

Hi

I have never used it but maybe this could do the job, here is a link from Cadence Support:
Voltus-Fi Custom Power Integrity Solution XL User Guide -- Structural Analysis - Missing Via Connections

Otherwise you could write a SKILL script parsing cellview nets and check pairs of layers that can be connected by vias

Another solution would be to run the SKILL equivalent of autovias: viaGenerateViasFromShapes with the connectShapesOnSameNet toggle enabled
(you can also use the netNames parameter to filter the nets for which you want to create vias)
You could parse the function output to delete the generated vias but keep their position
Be careful as this feature is not working properly in 6.1.7 releases but has been fixed since 6.1.8

I have no idea how long those scripts would run depending on the size of your cellview...

Cheers,

Aurélien
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mctang21 over 3 years ago in reply to AurelBuche

HI Aurelien,

Thank you for your info. I will try viaGenerateViasFromShapes with the connectShapesOnSameNet toggle enabled

Thanks,

ManChak
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mctang21 over 3 years ago in reply to AurelBuche

HI Aurelien,

Thank you for your info. I will try viaGenerateViasFromShapes with the connectShapesOnSameNet toggle enabled

Thanks,

ManChak
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