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  3. SKILL code for change pin names in symbols and schematics...

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SKILL code for change pin names in symbols and schematics for an entire library

Johanny Saenz
Johanny Saenz over 3 years ago

Hi all.

I have imported a stdcell library and the verilog to schematic generator gives me global power pin names. I would like to change them from VCC!,GND! to the VCC and GND for schematic and symbols in  an entire library.

How could I do it in SKILL?

Thanks

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  • Andrew Beckett
    Andrew Beckett over 3 years ago

    Without seeing an example of the Verilog you're importing, I'd not want to suggest an approach (I don't have code to quite do this; I have something to convert globals in imported schematics into inherited connections, but that's not what you're saying here - I'd like to see something that produces global pins). I'd experiment myself, but that would take more time and I'd just be guessing what your data looks like.

    Can you share some of the Verilog (of course, you might want to change it or remove some of the detail to avoid sharing IP)? If not, please contact customer support.

    Andrew

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  • Johanny Saenz
    Johanny Saenz over 3 years ago in reply to Andrew Beckett

    Hi Andrew.

    Thanks for your answer.

    My verilog has modules and std cells and looks like

    main module

    module COUNTER (
    CODE_CLEAR,
    CODE_CLK,
    CODE,
    VCC,
    GND);
    input CODE_CLEAR;
    input CODE_CLK;
    output [7:0] CODE;
    inout VCC;
    inout GND;

    Std cells definitions:

    module DLY1 (
    O,
    I,
    VCC,
    GND);
    output O;
    input I;
    inout VCC;
    inout GND;
    endmodule

    Std cells connections:

    DFFRBN \cnt_rst_reg[0] (
    .Q(cnt_rst[0]),
    .QB(n_6),
    .D(FE_PHN617_n_6),
    .CK(CTS_101),
    .RB(FE_OFN5_n_1),
    .VCC(VCC),
    .GND(GND));

    Is this what would you need?

    Thanks, Andrew.

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  • Andrew Beckett
    Andrew Beckett over 3 years ago in reply to Johanny Saenz

    Yes. I constructed a sample Verilog file based on what you provided, and by default I get VCC (not global) and GND! (global) pins. That can be fixed by going to the Global Nets tab of the File->Import->Verilog form:

    Change the ground net name to something other than GND!, and leave the Power net name as VDD! (I assume that you were setting it to VCC!). Then it won't mess with the pins and leave them as VCC/GND and this means you don't need SKILL to change them from global to non-global.

    At least this is the behaviour in IC6.1.8-64b.500.24

    Andrew

    Andrew

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  • Johanny Saenz
    Johanny Saenz over 3 years ago in reply to Andrew Beckett

    Thanks, Andrew.

    It did work. 

    In my opinion, strange behavior that you have to change the ground net.

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  • Andrew Beckett
    Andrew Beckett over 3 years ago in reply to Johanny Saenz
    Johanny Saenz said:
    In my opinion, strange behavior that you have to change the ground net

    Not really, since the whole point of these options is to specifically ensure that the power/ground nets are global if they match the names (without the !) on the form. You just need to change the default to something else so that it doesn't interfere with your pin you want to keep being called GND.

    Andrew

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