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override maximum FET length in schematic pcell to match layout MOSCAP dimensions

tdtg

We have a pesky properties mismatch in LVS because in our supply bypass cell, our drawn MOS cap dimensions cannot be matched by the PDK pcell FET maximum dimension. We are sure the device is OK (it is a MOS cap and we don't care about maximum frequency or something like this that would be affected by fab-specified max W and L for a FET). When we try to set the FET length to match the drawn (primitive) geometry it needs to be longer than the maximum length FET allowed by the pcell.

How can we override the maximum?  We can clearly match a desired width by parallel FET, but not length by series, since LVS says the series FETs don't match the drawn single FET.

Screenshot attached. This cell has 11 MOScaps and also two MIM caps (hidden in layout). The drawn dimension is W/L=145/25 um

Trying to change shows in CIW:

*Warning* Gate Length (l) value: 25.0 exeeds the upper limit of 10.0

Parameter value is set to its max value!

Version ICADVM20.1.64b.500.23 of Layout XL

for each of the 11 FETs. The maximum length we can set for pcell nmos33 is 10um.

  • This is generally not a good idea, because you may get some inconsistency - and whether it works or not will depend upon how the underlying PCell has been implemented.

    You can select the instance, and then invoke geQuerySelSet() . Then you can change the PCell parameters directly without triggering any CDF callbacks which might have been limiting the values. Of course, if you do this, then any dependencies will also not be computed either - and so what you do may not make sense. It's also possible that the PCells themselves might also limit the maximum size - in which case this won't work.

    Probably you'd need to contact the provider of the PDK because the precise behaviour is down to how it's been implemented for the particular PDK in question.

    Regards,

    Andrew

  • in reply to Andrew Beckett

    Thank you Andrew, that did the trick. The FETs in our cell were drawn in primitive layers. We just want schematic FETs to match them in size for LVS. We have not instantiated the FETs from the schematic.

    This is a useful tip, thanks again

    Tobi

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