abGenericDACFromTemplate.il in AMS flow

Hi, Dear Andrew Beckett,

I am using "sub-version  ICADVM20.1-64b.500.27 ." I followed your instruction in https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V00000911TpUAI&pageName=ArticleContent to create the pcell symbol with a verilogA view and a variable width bus. There is no problem to use it in a pure analog simulation from ADE Explorer by Spectre Version 21.1.0.484.isr11. When I bind it to verilogA view in a config and use it in AMS by simulator xrun 22.03-s005, I got the following error message from the netlister:

    ERROR (SFE-23): ".../netlist/analog/input.scs" 16: The instance `I40' is referencing an undefined model or subcircuit, `genericDAC'. Either include the file containing the definition of `genericDAC', or define `genericDAC' before running the simulation.

In order to debug this issue. I instantiated a non-pcell ahdllib/adc_8bit/veriloga symbol beside genericDAC in the testbench schematic.

The generated netlist analog/input.scs contains this line while it does not contain anything about adc_8bit.

      I40 ( net3 net1_7 net1_6 net1_5 net1_4 net1_3 net1_2 net1_1 net1_0 net2 ) genericDAC bits=8 fullscale=1.8 td=0 tt=0 vdd=1.8 thresh=0.9

The adc_8bit veriloga is mentioned in textInputs file:

      -amscompilefile "file:${AMS_CIC_HIER}/tools.lnx86/dfII/samples/artist/ahdlLib/adc_8bit/veriloga/veriloga.va ftype:va lib:ahdlLib cell:adc_8bit view:veriloga"

Is there any AMS netlister and CDF SKILL code that need to be added to your code in order to use the verilogA view in the AMS simulation?

By the way, I had a CCR #2566221 to add a systemVerilog view to the genericDAC cell to be used by the standalone runsv. It was fixed in ICADVM20.1.500.23. A Virtuoso crash happens when I try to add a systemVerilog view to generericDAC cell and do a "Extract" in the systemVerilog text editor in ICADVM20.1-64b.500.27. A new CCR 2751767 was created for this. These CCRs usually takes months to be fixed if they get high enough priority. These CCRs have nothing to do with the above question about using genericDAC/verilogA in the AMS simulation. I believe you should be able to whip up a quick solution to enable me to use  genericDAC/verilogA in the AMS simulation with the Virtuoso version that I am tied to.

Thank you very much in advance!

TJ