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How to solve the Backannotation problem in Virtuoso LayoutXL

Jinhyung

Thank for your interest.

Now, I'm using the LayoutXL, and trying to use 'Backannotation'.

I have 3 problems with backannotation.

1. Problem with mulit factor

In the .cdsenv file, I wrote those 3 comments. 

- layoutXL     lxDummyBackAnnotateMFactor     boolean     t

- layoutXL     lxDummyBackAnnotateMFactorName     string     "m"

- layoutXL     lxDummyBackAnnotateMissingTerm     boolean     t

So, if I click the 'Backannotate All Dummy Instances' after making 2 dummy transistors in my layout view, then it shows the transistor symbol with mulit = 2 in schematic.

However, if I make one more dummy transistor in the layout view after the preceding backannotation, it didn't show it as mulit =3 in schematic.

It shows 2 transistor symbols which are multi factor = 2, multi factor = 1 seperately.

Is there any solution for this problem?

2. Incorrect instance property with backannotation

The instance property doesn't match with dummy transistor in layout and in schematic after backannotation.

For example, I made the transistor with 'Length = 1.11um, width = 1.5um'. But, when checked the schematic after backannotation, there is the dummy transistor with 'Length = 1.2um, width = 2um'

Is there any solution for this problem?

3. Cannot make multiple number of dummy transistor at once.

I tried to make 4 dummy transistors. So, I select the original transistor, click the right mouse button, click the 'Create Dummy With Net', and press the F3 key to open the option browser.

I fix the following option

'Copies -> Number = 4'

Then, I returned to layout view, and clicked the view. But, when I clicked the view, dummy transistors aren't created.

I found that if I want to make 4 dummy transistors with 'Create Dummy with Net', then I have to execute 'Create Dummy with Net' 4 times.

Is there any solution for this problem?

Thanks for your time!

Regards.

Parents

  • Re...

    1) This is expected functionality. The operation will not seek out existing dummies in the schematic and modify the 'm' factor. To achieve the result you want, delete the existing dummy in the schematic and backannotate again.

    2) This should not happen. Is the device part of a Modgen? There are options to set different defaults for the dummy parameters.

      modgenDummyWidthOptions & modgenDummyLengthOptions

      If the issue persists please contact Cadence Customer Support.

    3) I note that the 'F3' (Command Option) invokes the standard 'Copy' command options. I validated the issue and consider this a bug. I will file a CCR.

  • in reply to RobMan

    Thanks for your time!

    I understood about 1), 3) answer.

    I think I need to talk a liitle bit more about the 2) problem

    This problem only occurs when I use 'freezepcell'. 

    I make freezepcell and binds it with Schematic. Then, I execute 'Create Dummy with Net', dummy transistor is created, and backannotation works.

    However, the length and width value of the schematic don't match with the dummy transistor in layout.

    Is there a solution for this problem?

    Best regards.

Reply
  • in reply to RobMan

    Thanks for your time!

    I understood about 1), 3) answer.

    I think I need to talk a liitle bit more about the 2) problem

    This problem only occurs when I use 'freezepcell'. 

    I make freezepcell and binds it with Schematic. Then, I execute 'Create Dummy with Net', dummy transistor is created, and backannotation works.

    However, the length and width value of the schematic don't match with the dummy transistor in layout.

    Is there a solution for this problem?

    Best regards.

Children
  • in reply to Jinhyung

    Hi ,

    Let me first elaborate on '3'. I investigated this further. If you check the CIW after the operation you will see,,,

    *WARNING* (LX-3116): Dummy creation was canceled, possibly due to the use of advanced copy options that are not supported for dummy creation, such as the Copy command accessed using F3.

    Quite simply; this functionality is not supported.

    Re. 2:You did not mention the use of 'Freeze Pcell'. This is no longer a pcell. The schematic master of this (new  layout cell) does not exist so a dummy should not be created...

    *WARNING* (LX-2002): Cannot create schematic instance for layout instance 'Dummy_I73' because there is no schematic master defined.

    Rob.

  • in reply to RobMan

    I'm really sorry that I didn't tell you about the freezepcell. 

    Actually, if you set the Layout XL environment variable 'lxDummyBackAnnotateMissingTerm' -> True in cdsenv editor, then you can create the dummy with freezepcell. The default value of the environment variable 'lxDummyBackAnnotateMissingTerm' is 'nil'

    So, after changing the environment value, making the freezepcell and finishing the "Configure Physical Hierarchy(CPH)", I click the freezepcell, do the 'Create Dummy with Net' and backannotate it.

    Then the schematic creates the dummy transistor successfully, but schematic displays the wrong value of dummy transistor's length and width in Layout.

    I think schematic recognizes the freezepcell dummy, but doesn't recognize the length and width of the freezepcell.

    Is there any solution....?

    Always thanks for your time.

    Best regards.

  • in reply to Jinhyung

    I don't believe the behaviour you experience is connected to these settings. I suspect you are using an old version of the software (pre IC618ISR25). Prior to this release a property was added to the dummy device (lxDummyOwner). This links the dummy device back to the source design device. With this information the dummy backannotation can refer back to the source for the schematic dummy. However, this proved troublesome as in many cases users copied dummies and used them throughout the design. The 'lxDummyOwner' was not correct or relevant. This property has been removed. Please check if the dummy derived from the frozen pcell has this property. The value is the instance name.

    So pre ISR25 the dummy backannotation will work. However, the frozen source layout device is no longer a pcell. Hence the parameters are not inherited by the backannotated schematic dummy.

  • in reply to RobMan

    Well, I'm using the IC618-ISR16, and so I used  IC618-ISR26, and tried to retry it. But, it didn't work again.
    I think when I make a freezeocell, then there is no parameter value in the edit properties which original pcell has. So, virtuoso didn't recognize it. 
    I have to try it personally... 

    Really thanks for your time.

    Best regards.

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