• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC SKILL
  3. [Spectre netlist] How to contain/have all the subckt definitions...

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 144
  • Views 1423
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

[Spectre netlist] How to contain/have all the subckt definitions of sub-blocks and devices included in a top level cell inside the top level subckt definition ?

MFahmy
MFahmy over 2 years ago

Hi, 

I am facing an issue where one possible solution would be having a self contained subckt definition in a spectre netlist

issue description: 

I have a testbench with Blocks : blockA and blockB , I am using alternative netlists of blockB and including those in the stimuli file using the include statement, during netlisting the primitive transistors gets the same subckt name but with -what seems to be - a random suffix 

if I have blockB netlisted enough times, I start getting subckt definitions for the primitive transistors which are colliding with the definitions in BlockA 

one way to address this would be to have subckt definitions which are local to netlist of blockB, is this possible? either local to the file, or local to the subckt definition of blockB or any other suggested solutions 

the netlists are created using the createNetlist() command 

Virtuoso version ICADVM20.1-64b 05/11/2023 
Sub-version ICADVM20.1-64b.500.28.EHF13629

Thanks, 

Fahmy 

  • Cancel
  • Andrew Beckett
    Andrew Beckett over 2 years ago

    Fahmy,

    It's not clear what exactly you're doing. However, perhaps using the MTS (multi-technology support) mode in ADE would help you - this will create scoped netlists. I've not tried (and don't have time right now) to test how you might do this from an OCEAN script (I'd start by doing it in ADE and then saving an OCEAN script).

    Andrew

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • MFahmy
    MFahmy over 2 years ago in reply to Andrew Beckett

    Thanks for the prompt response, I think my initial explanation was indeed not very clear (I will try to rephrase below)

    The MTS/scoped netlists sounds like a potential solution, is there a way to create a scoped netlist for all instances, i.e all of the subckts definitions are placed inside the top level subckt, alternatively, I can achieve the same by post processing the netlist and make sure that all of the subckt definitions are moved inside that of the top level, any expected drawbacks ?

    back to the issue itself, the netlister in the PDK I am using is assigning random/varying names to the pcells' subckt definitions of the primitive devices during netlisting, so as an example if I have 3 nmos transistors in the design [I0, I1, I2] they will get assigned to subckts called "transistor_subckt_15", "transistor_subckt_16", "transistor_subckt_22" , if the design is re-netlisted those subckts names will change, which is not an issue as the instances will point to the new subckt names correctly, but things started going wrong in my case because I am including an additional netlist which in some cases ended up containing one or more of the names are already used and point to a completely different device, the subckt "transistor_pcell_15" could be pointing to a a low leakage nmos in the first netlist, and a high speed pmos in the second netlist !

    Thanks, 

    Fahmy 

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information