generate a netlist of schematic designed in spectre.

rtyuy said:

cadence virtuoso IC6

That's not very specific. IC6.1.0 came out in 2006 - and IC6.1.8 was release in 2018 and is still having updates now. So that means it could be a version any time in the last 17 years.

You can generate an HSPICE netlist using the hspiceD simulator in ADE (or there's an integration available from Synopsys too). 

I don't really understand why wanting to generate a netlist for HSPICE is a consequence of the initial statement (I'm not sure why you would think that would be quicker, but then again it's far from clear what your issue actually is).

Andrew

thank you for  the response,  its IC6.1.8

well in my simulation i am running 128*128 sram array  instances (apprx 16000) and  overall  transient time for this simulation is very large .say i am taking time period 1ns for each instance operation. so for monte Carlo simulation (for 500) iteration) , run time is increasing more. so i am looking for less time taking process.  what else suggest to run monte Carlo .

Dear rtyoy,

rtyuy said:

i am running 128*128 sram array  instances (apprx 16000) and  overall  transient time for this simulation is very large .say i am taking time period 1ns for each instance operation. so for monte Carlo simulation (for 500) iteration) , run time is increasing more. so i am looking for less time taking process.  what else suggest to run monte Carlo .

Without knowing the details of your simulation, your circuit or your objective, I can only guess you are trying to assess the yield or number of failures expected due to random mismatch effects in an SRAM during a read or write operation. I also don't understand exactly what you mean when you stated "I am taking time period 1ns for each instance operation".

Nevertheless, I know there have been efforts to estimate impact of mismatch on SRAM performance without the need for a conventional set of transient Monte-carlo simulations. One such example is shown as reference [1]. In this paper, the author's conduct Monte-carlo analyses on the SRAM cell, the sense amplifier and bit line topology separately and combine the results to estimate the overall SRAM array variation in performance in the presence of random mismatch. Their results correlate well with the conventional Monte-carlo simulation they performed of the entire SRAM. Once again, without knowing your circuit, test bench, and goal, this may not be helpful, but wanted to at least mention it.

Shawn

[1] H. Nho, S. -S. Yoon, S. S. Wong and S. -O. Jung, "Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 55, no. 9, pp. 907-911, Sept. 2008, doi: 10.1109/TCSII.2008.923411.

i want to perform monte Carlo simulation of sram array , however it is taking lot of time. for 500 points of MC ,it is taking 7--8 hours .Any other way through simulation to perform the monte Carlo with less time?

You could run the Monte Carlo with multiple jobs which allows the points (or blocks of points) to be run in parallel. Another thing that could be consider is to use Spectre FX to accelerate the simulation since FX supports acceleration of SRAM (whether you have access to Spectre FX, I don't know - you should contact your account team to check). Otherwise, are you using Spectre X? Are you using multi-threading? Contacting customer support would be a good idea here for advice since you haven't give much information to go on...

Andrew