VIA enclosures alternating in VIAstack

I am trying to set up a constraint group for the vias used in my project, depending on track width, but the issue that appears is that due to different rules being defined (for wider tracks equal enclosure would be preferred, so (x x), while for narrow tracks end of line enclosure would be preferred, so (0 y)), I end up with VIAs like on the picture below; Mx enclosure is using the rules in one direction, while My uses it in the other direction. 

To give an example, my definition goes like this:

( minOppExtension "M3" "VIA2"

(("width" nil nil))

(0 ((0 Y)

0.18 ((X X)))

)

Is there a way to have the same enclosure for both metals (even if the via gets a small offset)?