Question on Skill Code for Cadence Official MOS PCell

As far as I'm aware there's no such thing as a "Cadence Official MOS PCell". I can only assume this is some sample that's been provided (I don't recognise the code and a bit of searching hasn't allowed me to locate it). The reason why there would be no "Official MOS PCell" is that technologies are often different so having a one-size-fits-all would be unlikely...

I suggest you ask your questions to whomever from Cadence provided you with the sample code.

There's no problem with having if(condition then then_code else else_code) even if the then_code is empty (it's a bit odd having the then keyword if you don't have any associated code - I'd probably just have used unless instead). For the rest of the questions I couldn't answer without seeing the rest of the code (and even then I'd need to know the intent - hence my suggestion for you to contact the person who provided you with the example).

Regards,

Andrew

Steve,

Thanks for the reference. I've not looked at those samples for many years (I think they were written almost 30 years ago).

I'll take a look during today and then can hopefully answer your questions having inspected the full code.

Regards,

Andrew

OK, I took a look.

The code is fairly complicated - it contains a whole load of infrastructure to install and configure various devices by adding extra information into your tech file and then installing the devices in the tech library too.

To set up, you'd use:

setSkillPath(cons(prependInstallPath("samples/ROD/rodPcells") getSkillPath()))
load("install/spcLoadInstall.il")

and then interact with the UI. You have to select the devices you want, choose the appropriate layers to use, and then fill in any missing design rule info that can't already be found in the tech file (sometimes these might be because of table rules).

The code is not being maintained and it's just a sample - whether you'd want to start from this or not is another matter. I'd probably recommend using PCell Designer instead if you can get access to it  - see this video: Creating a Simple MOSFET with PCell Designer

To answer your questions:

1. It's a little unusual, but having an empty then within an if/then/else is OK. It potentially makes it simpler to edit in the then part if you decide you need it later.
2. The rightStretch and leftStretch parameters are hidden parameters which are then altered by the abutment function when two transistors are abutted. If you've chosen to have the substrate contact enabled at the top/bottom, it may have to adjust the size of the diffusion to allow for these substrate contacts, but it only really needs to do it on one side - and in this case the right side is used.
3. This is (I think) trying to handle the scenario where the substrate contact protrudes beyond the transistor width (in this case it's the overall width of the device, not the width of the gate). That's where you'd have a problem with the substrate contacts hitting each other otherwise, so more space needs to be allowed.

Hope that helps!

Regards,

Andrew

Hi Andrew,

Thank you so much for taking the time to look into this and give such a detailed explanation!

Now I understand the big picture: this sample has a complete framework to add device definitions into the tech library. I also get why the code only adjusts rightStretch for substrate tie abutment. That makes sense now.

I will check out the PCell Designer video you shared.

Thanks again for your patient help!

Best regards,
Steve

Hi Andrew,

I came across a new problem when going over the code and hope to get your input.

Code segment with questions (from Cadence official):
;; Route poly if needed
when(routePoly && routePoly != "FALSE" && numberOfFingers > 1
     strap_width = ((numberOfFingers - 1) * gatePitch) +
               transistor_length
     strap_offset = gate_Extension - diffusionGateSpace
     polyfig = rodCreatePath(
        ?cvId cellViewId
        ?layer gateLayer
        ?width minPolyWidth
        ?pts list(0:0 strap_width:0)
        ?termName "G"
        ?pin t
        ?termIOType "input"
     )
     cond(
         ( routePolydir == "Top"
           rodAlign(
              ?alignObj polyfig
              ?alignHandle "lowerRight"
              ?refObj topPin
              ?refHandle "upperRight"
              ?ySep -strap_offset
              )
         )
         ( routePolydir == "Bottom"
           rodAlign(
              ?alignObj polyfig
              ?alignHandle "upperRight"
              ?refObj botPin
              ?refHandle "lowerRight"
              ?ySep strap_offset
              )
         )
     )
     polyfig~>dbId~>pin~>name = "gatePin"
     spcClearGatePins( gatePins )
)

My Questions:

My question: I understand that strap_offset is used to meet DRC requirements. However, if the value of diffusionGateSpace is larger than gate_Extension, wouldn’t that mean polyfig is not placed right next to topPin / botPin? They would be separated by a distance of |strap_offset|. The intended behavior is that all gates (in the multi-finger case) are connected together by polyfig. This is where I’m confused.

Best regards,
Steve

Yes, that's correct. You'd have seen that if you'd tried it (which is what I did). It's clearly an assumption in the code (trying to cater for every possible scenario is hard, and in most technologies I've seen the gate extension is larger than the poly to diffusion spacing so it probably didn't get caught in testing when this sample was created almost 30 years ago. It is a sample after all - not guaranteed to be perfect.

I’ve only touched PDK (Skill/PCell) for half a year and haven’t systematically learned process knowledge and Skill coding. So I’m using these PCell codes as my entry point for structured study. Despite some bugs, they let me understand the general framework. Haha, I still need to learn much more about process and Skill.

I’ve only touched PDK (Skill/PCell) for half a year and haven’t systematically learned process knowledge and Skill coding. So I’m using these PCell codes as my entry point for structured study. Despite some bugs, they let me understand the general framework. Haha, I still need to learn much more about process and Skill.