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NanoRoute: DRC / LVS issues

kulprashant

Hi,

I have completed the routing using Nanoroute and the in the summary report, there are no LVS violation and few DRC violation(~50).

I saved the design and then from GUI, i check the DRC with all option (command : verifyGeometry with default option), then i was shocked by looking towards results, there thousand of violations and lot of process antenna violation(~100).

1, how it is possible? nanoroute has not dumped correct report or is thier any other issues?

2. In DRC, i have checked, there are similar violation (almost all are same) and the DRC errors are spacing violation with same net?

                                 exa: spacing vioaltion : metal: M3  actual =0.5   min =0.7

what is meaning of this and how to solve this type of issue (same type of violation with M2 & M1).

3. I found some max transition and max fanout violation, how to solve these violation at this stage? (because solving these vioaltion nothing but adding or sizing the buffers at placement level, it means  i have to do once again CTS and routing ) or any other method to solve or ecos??

Thanks & Regards,

Kul   

  •  Hi Priyatham,

    Have you run a signoff DRC on this design? Does it find the same violations that Verify Geometry does? If not, then the violations are not real and it's probably a VerGeom setting that needs tweaking. If so, then we need to investigate further.

     - Kari

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