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Can CTS stop tracing on hierarchical module ports?

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Dear community,

my clock signal is connected to the clock network on the one hand. On the other hand it is connected to a module's input. Within this module the signal is always used as a data signal (chip is switched to different mode of operation for this).

This module contains logic, therefore CTS traces through the input ports. AFAIK tracing can only stop at top level ports or leaf cell pins.

Is there any way to make CTS stop tracing at the module's input port (like ExcludedPin/ExcludedPort - which don't work)?

Many thanks in advance for your suggestions!


Originally posted in cdnusers.org by agruebl

  • Bob:

    I just attended the SOC-E 71 Release seminar. It is great that you give a living example of how to use dbGet.
    Many Thanks!

    Best Regard


    Originally posted in cdnusers.org by eminemshow

  • ...and here's my solution. I've done it with Sy****ys-TCL and this code is called directly after Synthesis. A .ctsh file with a "special" format containing the hierarchical port definitions is parsed and the output is written to the .ctsh file used by CTS.

    set repl_trigger "REPLACE_"
    set rootpin      "AutoCTSRootPin"
    set infile [open $CTSINFILE]
    set outfile [open $CTSOUTFILE w]
    set data [read $infile]
    set lines [split $data \n]
    set replace false

    foreach port $lines {       
    # parse input lines
        set pstart [string range $port 0 7]
        if {$pstart == $repl_trigger} {       
    # the port definitions following this line will be replaced
            set replace true
            set out [string range $port 8 end]
            set outtype $out
            if {$out != $rootpin} {       
    # the RootPin needs to be defined in the same line as the according statement...
                puts $outfile $out
            }
        } elseif {$replace == true && [string index $port 0] == "+"} { 
    # replace port name with pin name(s)
            set aport [string range $port 3 end]
            if {[string index $port 1] == "i"} {       
    # replace input leaf pin names
                set inpins [get_pins -filter "@pin_direction == in" -hierarchical [all_connected [get_nets $aport]]]
                set prefix "+ "
            } else {       
    # replace output pin names
                set inpins [get_pins -filter "@pin_direction == out" -hierarchical [all_connected [get_nets $aport]]]
                if {$outtype == $rootpin} {
                    set prefix "$rootpin\t\t"
                } else {
                    set prefix "+ "
                }
            }
            if {[get_object_name [get_nets $aport]] != ""} {
                foreach_in_collection pin $inpins {
                    set out "$prefix[get_object_name $pin]"
                    puts $outfile $out
                }
            }
        } else {       
    # line not relevent - forward to output
            set replace false
            puts $outfile $port
        }
    }

    As all regular code in the input .ctsh file is forwarded to the output file, hier. port definitions and correct pin definitions can be mixed. :-)


    Originally posted in cdnusers.org by agruebl

  • Thanks for all

    This info gave me a lot of new things about CTS


    Originally posted in cdnusers.org by mahecadence

  • hi eminemshow
    please can you tell me the difference between clock buffers and normal buffers


    Originally posted in cdnusers.org by mahecadence

  • Posted By mahecadence on 11/20/2007 4:00 AM
    hi eminemshow
    please can you tell me the difference between clock buffers and normal buffers
    I think the main difference is that clock buffer & inverter have nearly equal rising & falling delay.


    Originally posted in cdnusers.org by eminemshow

  • Thanks


    Originally posted in cdnusers.org by mahecadence

  • Many Thanks


    Originally posted in cdnusers.org by mahecadence

  • Many Thanks to


    Originally posted in cdnusers.org by mahecadence

  • many thanks eminemshow, can you explain me this by an examle


    Originally posted in cdnusers.org by mahecadence

  • without equal rise/fall delay, the duty cycle (started with 50/50) will get distorted going thru the unbalance buffer. It should bot affect the flops operation which trigger off the rising edge but some ram designs trigger off the falling edge. Inverter can slef-correct the unbalance rise/fall due to it inverted nature. So inverter is a better choice to use in a clock tree to prevent duty cycle distortion.

    li siang


    Originally posted in cdnusers.org by lisiang

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