Dear All:I want to know what is the default input transition for register clk pin during preCTS stage. I have read the user guide, got nothing. But from the timing report, I can see different registerCLK -> Q delay. It is load & clock transition dependent, I can get the load, but how can I get the transition. This is critical for preCTS & postCTS timing correlation. Moreover I don't have set_clock_transition command in my SDC file.Or is there a virtual CTS stage which can make SOC-E know the 'will-be' register clock pin input transition?Many thanks
Is this the variable ui_in_tran_delay in the donfig file that you are looking for?http://sourcelink.cadence.com/en/search/DisplayHtmlDoc.jhtml;jsessionidsl=ON3JVX4XPGDLFLA0BEASFEQ?param1=http://sourcelink.cadence.com/docs/db/kdb/2007/June/11341160.html?param2=null?param3=Solutions?param4=11341160?param5=/software/cadence/sldocs/db/kdb/2007/June/11341160.html@en_col?param7=How%20to%20set%20transition/slew%20at%20input%20pins%20of%20clocks%20for%20CTS?Sanjay
Sanjay: Many thanks! Sanjay, what you said is right!Best RegardMy msn is email@example.comHope we can be friends.