Different voltage for bulk pins of logic gates

 Hi,

In the standard cell library characterization using ELC tool, the tool automatically ties the bulk of PMOS to VDD and that of NMOS bulk to GND. Is their any provision or command so that the users can give a separate voltage to the bulk of NMOS and PMOS and do the library characterization.

 I tried to use signal command defining a new volatage level and assign the signal to the bulk pin group in the set signal statement but did not work.

Berifly let me give my setup file:

//Define section

Process nom_1.10V_25C {
    voltage        = 1.1    ;
    temp         = 25    ;
    corner        = "TT"    ;
};

Signal HS45LP_signal {     
    unit     = REL ;
    Vh        = 1.1 ;
    Vl        = 0.0 ;
    Vth        = 0.4 0.6 0.4 0.6 ;
    Vsh        = 0.8;
    Vsl        = 0.2;
    tsmax    = 1n;
};

Signal VDDS {
    unit    =    ABS;
    vh    =    1.5;
    vl    =    0;
    tsmax= 2.0n ;

};

Group VDDB {
pin    =   *.vdds;
};

// ************************************************
// ***                CONTROL SECTION                ***
// ************************************************

set process (nom_1.10V_25C) {   
    simulation            =    HS45LP_simulation    ;
    margin                =    HS45LP_margin        ;
    nominal             =    HS45LP_nominal        ;
    signal                =    HS45LP_signal        ;
};

set signal (nom_1.10V_25C) {
Group (VDDB)    =    VDDS;
};

This was the statements used in the set up file to give a differnt voltage to the bulk of PMOS. Instead the tool is always taking the process voltage and not taking teh signal volatge.

 Can any one let me know, how to solve the issue.

 Thanks in advance,

 Regards,
Sandeep