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how to varies the threshold voltage for mos transistor??

hai,

am using cadence virtuoso for my project. Here I got a problem about vth in my ieee base paper they are using high vt and low vt transistors .

In my library I also had low vt and high vt trasistors. But base paper guys are used some low vt at 0.22V for p&n mos high vt 0.466V .

Come to gpdk045 library I have high vt transistors at 0.731V for nmos and 0.6V for pmos low at some 0.4V. So please tell me how reduce the vth in virtuoso?

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