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"block based" sparse memory

This is another sparse memory model with an interface similar to shr_ram. It attempts to improve performance by reaching a compromise between a flat implementation (used for fully/mostly implemented memories) and a keyed list implementation (used for very sparsely implemented memories) by using dynamically sized blocks to represent implemented regions. See the user guide and examples for details.

Originally posted in cdnusers.org by spadix

csco_blk_memory_version_1_0.tar.gz

archive over 18 years ago

Is there something similar available in System Verilog also.
If yes, could you pprovide a example

Regards,
Parag

Originally posted in cdnusers.org by parag123
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