Community Functional Verification Shared Code Hold violation at post P&R simulation

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Hold violation at post P&R simulation

shahein

Hello,

 I am working in a digital design. The functional, post synthesis and post P&R without IO pads are all working fine, i.e., functionally and with clean timing reports "no setup/hold violations". I just added the IO pads to the same design, I had to change the timing constraints a bit for the synthesis but I have a clean design at SOC Encounter, i.e., clean DRC and clean timing reports "no setup/hold violations". However, when I perform simulation using the exported net-list from SOC Encounter together with SDF exported from the same tool, I got a lot of hold violations. Consequently, the design is not funcitioning.

Why and how I can overcome or trobleshoot this issue?

In waiting for your feedback and comments.

Regards.

  • Hey, Until now the design is communication internally and hence the timing was good, but once IO pads have been placed the data coming from outside block should communicate with your block pin or from block pin to a std cell in your design, that means a delay may arise in this scenario. So try using IO buffers or create some feed-through ports to your design so that data may communicate effectively. Hope this may give some idea.

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