Stats

  • Locked Locked
  • Replies 1
  • Subscribers 50
  • Views 13279
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Mix-Singal system verification using VHDL and Verilog-AMS, pls help

lagy

Our design is a mix-signal chip. It contains half digital part and half analog part.

In order to have a more accurate system verification, we intend to use Verilog-AMS for the analog model and VHDL as the chip top.

This is the first try for us to do such a verification.

Anyon has idea whether this scheme is applicable or not?

Any reference on similar implementation. 

Thanks and Best Regards

jh.

  •  hi there,

    it is very much possible to do what you are trying to do. use cadence ams designer for this purpose and its better you use verilog instead of vhdl, or you can use system verilog, systemc as top level module.

     

    regards,

     tr

     

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.