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backannotation in a hierarchical design

thescreen

 hi there

i am dealing with a multi-million gate, hierarchical design with a top level istantiating 6 large hard macro

i would like to simulate a top level micro interface (it is flattened in the top level netlist) communicating with each hard macro: in order to make the simulation not too much demanding in terms of memory and cpu suage, i'd like to setup a set of gate level simulation w/i backannotation using the top level netlist + HM<n>, leving the other HM(n != n) as black boxes

do you see any problem with that, before i have a try with this (I cactually do not have any DSF available)

i am concernet abot the boundaries between the top level and the had macro (the last piece of wire betwee th top and the HM boundaries are backannotated?)

many thanks

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