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verilogA to verilog translation

vlau2

Is there any utility (official or unofficial, crude or robust) to translate verilogA code to verilog, it doesn’t have to capture all the details but anything that can be translated will be helpful.

  • Verilog-A could be anything from abstract V/I assignment operations to primitive device instantiation and everything in between. It's not going to be a simple translation by any stretch. Can you be more specific about what's being modeled in Verilog-A and how the generated Verilog model is intended to be used?

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