NC-Verilog Co-simulation

I have some control software written in C++ that I am trying to interface with my Verilog RTL model.  I would like to co-simulate in such a way that the C++ runs interactively with the NC-Verilog session to control start, stop, and also to read/write net values on my RTL.  All of the information I have come across regarding a scenario like this turns to PLI/VPI to allow the Verilog to run C commands, which doesn't satisfy my needs.  I'm wondering if there is a way to have the simulator run under the control of an outside application interactively.  It seems like most designers turn to ModelSim to perform this but I want to know if there is a way to do it with NC-Verilog.

Thank you.