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C-to-Silicon

roel
Dear reader, For my PhD research I am currently comparing several C to VHDL/Silicon approaches and tools. We have set up a library of kernels and on this library we automatically run the DWARV c-to-vhdl compiler and the C-to-Verilog compiler from Israel. We were also considering doing the generation of hardware from CTOS, but it seems not straightforward to automatically run CTOS over a large set of C functions. Is there a manual describing how to use CTOS from the command line? Or is there some scripting manual that I may use? If not, is there any Cadence CtoS expert out there that can give me some pointers as to how I can automate generating hardware from many different functions. thank you very much in advance for any help you may provide. regards, Roel Meeuws, PhD Candidate Computer Engineering Dept. Delft University of Technology
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  • Hi Roel,

    Great topic for a PhD!

    The Cadence C-to-Silicon Compiler (CtoS) is fully documented in the 900 page Users Guide that ships in the install.  You can contact your local sales/AE for details.   We also have a University program that makes it available to some schools when appropriate.

    CtoS can take high-abstraction SystemC to generate functionally equivalent RTL-Verilog which will then easily synthesize to gates to meet timing (and be leq-able).   The main input language is SystemC, but CtoS also offers the capability to read in C/C++ functions in which you can then choose a built-in TLM lib interface/transactor and CtoS automates the generation of the SystemC wrapper.

    CtoS can be run via standard tcl scripts (very similiar to RC)  to automate many options/flows, but otherwise CtoS has a very different use-model than other HLS tools since we put a very large effort into having a powerful GUI that visualizes the design and offers many choices to try differing micro-archititectures, plus lots of analysis to compare and further refine to achieve optimal Quality of Results.

    hope this helps.

    -mark
Reply
  • Hi Roel,

    Great topic for a PhD!

    The Cadence C-to-Silicon Compiler (CtoS) is fully documented in the 900 page Users Guide that ships in the install.  You can contact your local sales/AE for details.   We also have a University program that makes it available to some schools when appropriate.

    CtoS can take high-abstraction SystemC to generate functionally equivalent RTL-Verilog which will then easily synthesize to gates to meet timing (and be leq-able).   The main input language is SystemC, but CtoS also offers the capability to read in C/C++ functions in which you can then choose a built-in TLM lib interface/transactor and CtoS automates the generation of the SystemC wrapper.

    CtoS can be run via standard tcl scripts (very similiar to RC)  to automate many options/flows, but otherwise CtoS has a very different use-model than other HLS tools since we put a very large effort into having a powerful GUI that visualizes the design and offers many choices to try differing micro-archititectures, plus lots of analysis to compare and further refine to achieve optimal Quality of Results.

    hope this helps.

    -mark
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