verilog testbench simulation

Hi,

I am trying to write and simulate my first code in verilog, but I can't simulate it. When I run simulation the chronograms stay empty .

My code is a simple 3-in AND gate:

module and3 (e1, e2, e3, s);

input e1;
input e2;
input e3;

output s;

assign s = e1 & e2 & e3;

endmodule

And below, the testbench I use:

`timescale 1ns / 10ps

module and3_tb;

reg e1_t, e2_t, e3_t;
wire s_t;

and3 and3( .e1(e1_t), .e2(e2_t), .e3(e3_t), .s(s_t) );

initial
begin

$monitor(e1_t, e2_t, e3_t, s_t);

e1_t = 1'b0;
e2_t = 1'b0;
e3_t = 1'b0;

#5

e1_t = 1'b0;
e2_t = 1'b0;
e3_t = 1'b1;

#5
e1_t = 1'b0;
e2_t = 1'b1;
e3_t = 1'b0;

#5
e1_t = 1'b0;
e2_t = 1'b1;
e3_t = 1'b1;

#5
e1_t = 1'b1;
e2_t = 1'b0;
e3_t = 1'b0;

#5
e1_t = 1'b1;
e2_t = 1'b0;
e3_t = 1'b1;

#5
e1_t = 1'b1;
e2_t = 1'b1;
e3_t = 1'b0;

#5
e1_t = 1'b1;
e2_t = 1'b1;
e3_t = 1'b1;

end

endmodule

I use ncvhdl/ncsim suit with incisiv, below its how I write the commands:

ncvlog -work work -message \
../modules/and3.vlog \
../modules/and3_tb.vlog

ncelab -cdslib cds.lib -hdlvar hdl.var -messages -access +r+w+c -update -timescale '1ns/10ps' -logfile ncelab.log work.and3

ncsim -gui -messages -nocopyright -log ncsim.log work.and3

So when I run ncsim, at the moment I choose the input/output of the module (e1,e2,e3,s here) the initials values are 'x', but when I compare with a simulation in vhdl these values are 'U'. So when this part is finish I run the simulation and nothing happens...

Can you help me please?