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Memory utilization

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Hi All,
I am trying to understand why IUS 5.83 utilizes more physical memory for REG datatype than BIT datatype. For example
`define    MAX_MEM    1048576*4
module    sv_test;
reg    [127:0]    memory[0:`MAX_MEM-1];        // unpacked
integer    i;
initial
begin
    for (i=0; i
     begin
      memory[i] = 0;
         end
     $display ("array data %d", memory[349]);
     $display ("array index %d", i);
end
endmodule

In this example, the array uses twice as much RAM since it is of type REG. Can some one please explain why this is so?

Thank you


Originally posted in cdnusers.org by sreeramr

  • In SystemVerilog, BIT is defined as a two-state variable, while REG is defined as a four-state variable. Since REG has twice as many states, it needs twice as much physical memory.

    Hope this helps!

    Dave Allen


    Originally posted in cdnusers.org by davea

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