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how to simulate ADC INL DNL with Cadence.

Hi everybody,
I have designed an analog 10 bits DAC in CMOS 018u techno with cadence. I want to simulate the schematics to obtain the INL and DNL. can Someone help me about that or give me a link where a Icould find more information ?? Is it possible with cadence or do i need to use another tool?

Thanks for Ur help...

Originally posted in cdnusers.org by isazul

archive over 18 years ago

there is a little mistake in the title as U see it`s not INL and DNL for an ADC but for a DAC

thks

Originally posted in cdnusers.org by isazul
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