Instability during simulation

Hi, guys

I'm experiencing some problems and I didn't find any way to solve then....

I have an edge detector, which works perfect in FPGA, but I cannot simulate it...

It was designed to be robust to setup/hold time violation, because when the sampling in the first flip-flop violates it, the clock period is long enough to resolve the output of the first flip-flop to the second one  (so the signal should be "1" or "0" at the output (rising or falling) and never "x").

When I simulate it without SDF file it works perfectly, becouse it doesn't handle with setup time violation, but when I include it simulation apears like the image above.

Anyone knows how to configure simulator to resolve the signal before the next period, as in "real world"...