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Cadence TBA prob

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Hi,
I am using the Palladium2 for emulation and am working in TBA mode. I see a lot of issues with VAP-
1. It is not able to compile memories which are fine in ICE mode.
2. It appears to have some problems with hierarchical referencing.
3. It gives strange errors in verilog rtl which go smoothly in DAA step of TBA
These problems exist in versions 3.1,4.1,5.0 of IXE

I would appreciate any comments in this regard.

Thanks,
Hemanth


Originally posted in cdnusers.org by hemanth

  • Hi Hemanth!

    I'm a Core Comp AE for TBA.  I may be able to help you with these problems.

    I'll need more detailed information on the problems.

    - Can you send me a sample of the memory RTL that's causing problems?

    - Can you describe the hierarchy that are causing the hierarchical referencing problems?

    - What are the strange error messages that you see from the Verilog RTL?

    Please contact me directly at davea@cadence.com

    Best regards,

    Dave Allen


    Originally posted in cdnusers.org by davea

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