Hi all, I have a basic question related to the the plane via clearance in allegro apd. I know the design has 50um via plane clearance, however, it is not defined in the via padstack and when I go on the global dynamic shape parameters, it shows DRC. I am having a hard time finding the rule, so I was hoping that someone can point me to the right location within the tool to look for this
If you open the constraint manager tool, and go to the spacing constraints, you should be able to find the via columns under the “shape to” section. This is where you’ll find the values, sorted by layer, that you’re looking for. When the shape global parameters is set to DRC, this is the value that is used for the clearance. You can create different net groupings, constraint regions (areas), etc. to customize the values between different nets, or in diffeeent areas of the board, not just on a per layer basis.
Let me know if you can’t find it there, and I’ll see if I can get some pictures to post for you. The table in constraint manager is large, but you’ll find it!