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  3. Issue with the # clocks while synthesizing DW02_mult_4_stage...

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Issue with the # clocks while synthesizing DW02_mult_4_stage component

sureshm
sureshm over 14 years ago

Hi all,

   In one of the design,  DW02_mult_4_stage has been used and multiple clocks ( 2 clocks from the top module -- mux convergence of two clocks ) are being fed to this instantiation...

while synthesize -to_generic phase of RC synthesis, Tool issues the below Error

Error   : The retimeable flops are clocked with different clocks. [RETIME-401] [synthesize]
        : The following clocks drive retimeable flops.
    non inverted /designs/retime_partition/timing/clock_domains/domain_1/MCLK (register: DW02_mult_4_stage_i/R_reg_3_9)
    non inverted /designs/retime_partition/timing/clock_domains/domain_1/PIX_CLK (register: DW02_mult_4_stage_i/R_reg_3_9)
    inverted     /designs/retime_partition/timing/clock_domains/domain_1/MCLK (register: DW02_mult_4_stage_i/R_reg_3_9)
    inverted     /designs/retime_partition/timing/clock_domains/domain_1/PIX_CLK (register: DW02_mult_4_stage_i/R_reg_3_9)
Error   : The retimeable flops are clocked with different clocks. [RETIME-401] [synthesize]
        : The following clocks drive retimeable flops.

Can someone help me understanding the issue in here?  

Is there something to do specially with the multi stage architechtures, that the tool will crib for the multiple clocks propagated and  how does it really different from other normal registers with multiple clocks being propagated to them .. ???

 Thanks in advance

suresh  

 

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  • grasshopper
    grasshopper over 14 years ago

     Hi Suresh,

     tools do not retime across logic on different clocks since there is no timing relationship to retime. Unfortunately, RC does not handle this automatically and instead gives you the warning you mention when you try to retimg a design with multiple clocks. In such cases you will need something along the lines of

     set_attr dont_retime true [all des seqs]

    set_attr dont_retime false all des seqs -clock...]

    ....

    you may need to perform multiple calls to retime command if need to retime multiple clock domains

     hope this helps,

    gh-

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